Tire temperature sensor schematic: concrete fixes before PCB layout

Fix these before you release the tire sensor PCB: quantify the sensing path (contact vs IR), bias the analog front end around your temperature band, cap self‑heating below 0.05°C, lock power‑up/TX to coin‑cell limits, and prove a 50 Ω RF feed with room to tune.

Contact or IR sensing for tire temperature?

If you need tread or liner surface without contact, use an 8–14 µm IR thermopile; assume rubber emissivity ≈0.95 and pick a narrow FOV (10–20°) so the sensor only sees rubber. Add a matte black baffle to reject reflections. For contact sensing, bond an NTC/RTD to the inner liner or rim using a high‑temperature adhesive (rated ≥150–200°C) and keep copper near the element short and thin to avoid heat sinking. Place a grounded guard around the analog node to cut RFI picked up inside the wheel.

NTC divider and ADC sizing near 80–120°C

A 10 kΩ, B=3950 NTC is ≈1.28 kΩ at 80°C. Bias with Rbias ≈1.3 kΩ on 3.3 V: Vout ≈ 3.3 × 1.28/(1.28+1.3) ≈ 1.64 V. Around 80°C, dV/dT ≈ 40 mV/°C; a 12‑bit ADC at 3.3 V (0.806 mV/LSB) yields ≈50 LSB/°C, leaving margin for noise and calibration drift. Add a single‑pole anti‑alias filter at the ADC pin; 1 kΩ + 1 µF gives ≈159 Hz cutoff. Decouple each IC with 100 nF within 1–2 mm of the power pin plus a nearby 1 µF bulk cap.

How do you keep NTC self‑heating under 0.05°C?

Excite with constant current in the 50–100 µA range. Example at 80°C: I=100 µA into ≈1.6 kΩ yields P≈16 µW. For a 1 mW/°C dissipation constant, ΔT≈0.016°C. Duty‑cycle measurements if you must push higher current; sample quickly, then power‑gate the divider.

Coin‑cell power, brownout, and motion wake

A CR2032 works if average current stays below ≈10–15 µA between short bursts. High‑side gate the sensor and RF with a P‑MOS to clamp sleep leakage. Set brownout ≈2.0–2.4 V and delay RF TX until Vbat recovers; coin‑cell ESR rises sharply below 0°C (tens of ohms at −20°C). For motion‑based wake, a MEMS accelerometer at 1–10 Hz ODR typically draws ≈1–5 µA; a reed/Hall switch is an alternative with nA leakage.

How do you route 50 Ω on 1.6 mm FR‑4?

As a starting point on FR‑4 (εr≈4.2), a 1.6 mm board with top‑layer microstrip over a solid ground plane needs ≈3.0 mm width for ~50 Ω. For coplanar waveguide with ground, 0.3 mm gap and ≈2.7 mm width is typical. Verify with a field solver; IPC‑2141 equations are first‑order. Keep a 3–5 mm ground/metal keep‑out around antenna elements and avoid unnecessary solder‑mask openings on RF traces.

Antenna placement and matching on a rim

Metal rims shield RF; placement dominates link budget. 315/433 MHz often propagates better from inside a tire than 2.4 GHz, but test your geometry. Reserve a π‑match (C‑L‑C) at the feed for tuning. Provide conducted test access (U.FL or coax pad) so you can characterize the PA and match before relying on over‑the‑air tests. Use a via fence around any layer transition of the RF feed and trim stubs during bring‑up.

ESD and mechanical survival targets

Design to IEC 61000‑4‑2 levels (±8 kV contact/±15 kV air). Place a bidirectional TVS at the battery input. Add 22–100 Ω series resistors and low‑cap ESD diodes on sensor and I²C lines. Tires can see >1000 g radial acceleration at highway speed; select −40 to 125°C ICs, X7R capacitors, and add corner staking or underfill for large/leadless packages. If you use conformal coat, choose neutral‑cure silicone or urethane; avoid acetic‑cure near copper.

PCB stackup and layout details that affect calibration

Use a continuous ground plane under the analog front end. Tie sensor ground to system ground at a single, quiet point; keep high di/dt returns away from the sensing node. If you pot, specify high‑Tg laminate, check CTE mismatch, and add vent paths to prevent bubbles over an IR aperture or NTC bead. For impedance control, request a TDR‑measured coupon and report; use the same glass style (e.g., 7628) and resin content in fab as in your stackup model.

Manufacturing and compliance specifics

Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria; call out the target class on your fab notes and include controlled‑impedance targets and test coupon requirements (TDR per IPC‑TM‑650 2.5.5.7 is common). RoHS and REACH compliance is supported; include material declarations and homogeneous‑material limits in your PO. HyperPCB operates an ISO 9001:2015 certified quality management system (certificate CN‑2023‑Q1156, SGS, valid to June 2027). Quotes are returned within 24 hours and DFM feedback within 1 business day.

Schematic review checklist

• Pick contact vs IR; document emissivity/FOV or thermal path/adhesive

• Compute Rbias or Iexc at the target band; add RC anti‑alias and ESD clamps

• Confirm ADC LSB vs mV/°C and reference tempco; define calibration points

• Set sleep currents, brownout threshold, and TX deferral vs coin‑cell ESR

• Reserve π‑match, 50 Ω feed geometry, and coax test access; define keep‑outs

• Place TVS at the battery; series resistors/ESD diodes on sensitive nodes

• Call out IPC Class 2/3, impedance targets, and coupon/test deliverables