4‑layer PCB vias: types, drill sizes, stackups, and DFM rules

On a 4‑layer PCB, you can use through, blind, buried, and microvias; choose the simplest span that meets routing, impedance, and reliability goals.

Via options on a 4‑layer PCB

Through‑hole vias (L1–L4) are the default for most 4‑layer builds. Blind vias (e.g., L1–L2 or L3–L4) and buried vias (L2–L3) are possible but require sequential lamination. Laser microvias (e.g., L1–L2) are used for tight BGAs or via‑in‑pad; they add cost and process steps versus a pure through‑via design.

Which vias should you use on 4 layers?

• Use through vias wherever fanout and density allow—they are robust, single‑lamination, and cost‑effective.

• Add blind L1–L2 or L3–L4 only when escape routing under fine‑pitch BGAs demands it.

• Reserve via‑in‑pad plated over (VIPPO) or laser microvias for dense packages; specify fill/plate/planarize if the pad will be soldered.

Common 4‑layer stackups and via spans

A practical 1.6 mm stack uses L1 signal, L2 solid GND, L3 power (split as needed), L4 signal. Through vias span L1–L4; blind vias commonly span L1–L2 and L3–L4; a buried L2–L3 link is sometimes used to keep planes quiet. Keeping L2 as an unbroken reference simplifies return‑via placement when signals swap layers.

Key via dimensions and clearances

• Board thickness: 1.6 mm typical for FR‑4 4‑layer.

• Finished mechanical via: ≥0.30 mm for robust plating; keep aspect ratio (board thickness / finished hole) ≤10:1.

• Annular ring (radial): ≥0.15 mm for general Class 2 targets; ≥0.20 mm for Class 3 targets.

• Pad size example: 0.30 mm finished hole + 2×0.15 mm ring → 0.60 mm pad.

• Drill‑to‑copper clearance (antipad to planes): ≥0.20–0.25 mm; via‑to‑board edge: ≥0.30 mm.

• Hole‑wall copper per IPC‑6012 Class 2/3: ≥20/25 µm; call this out in the fab notes.

• Laser microvias: 0.10–0.15 mm typical; keep depth/diameter ≤1:1 (≈0.8:1 preferred) for reliability.

• Solder mask: tent vias ≤0.30 mm to reduce solder wicking; specify epoxy plug/cap when needed (e.g., VIPPO or under thermal pads).

How do vias impact signal integrity?

Every layer change needs a local return path. Place a stitching ground via within 1–2 mm of the signal via, tied to the solid reference plane. Keep antipads just large enough to meet clearance while minimizing discontinuity. On 1.6 mm boards, a through‑via stub resonates around ~25 GHz, so it is usually benign below ~10 GHz; if you run multi‑tens‑of‑GHz, consider backdrilling or blind vias.

Thermal vias, current, and reliability

A single 0.30 mm via with 25 µm hole‑wall copper in 1.6 mm FR‑4 has ≈1.2 mΩ DC resistance (R ≈ ρ·L/A; A ≈ π·D·t). That is suitable for about an ampere of DC with modest temperature rise; parallel an array for higher current or for heatsinking. Under power devices, 0.30–0.40 mm vias on 1.0–1.2 mm pitch, tented on the component side and open on the opposite side, are a proven pattern to pull heat into internal planes or a backside copper pour.

Fabrication notes and acceptance criteria

Call out exactly which vias are through, blind, buried, or micro, and where you require tenting, plugging, or filled/capped VIPPO. Document target aspect ratio, finished hole sizes, annular rings, and hole‑wall copper, and reference IPC‑6012. We can build and inspect to IPC Class 2 or Class 3 acceptance criteria, and support RoHS and REACH compliance. Our ISO 9001:2015 certified quality management system (SGS certificate CN‑2023‑Q1156, valid to June 2027) governs production. For sourcing efficiency, we return quotes within 24 hours and DFM feedback within 1 business day.