How to choose PCB layer count, dielectric thickness, and impedance

Choose layer count from routing density and BGA pitch (1.0 mm pitch often escapes on 4 layers with 0.10/0.10 mm rules; 0.8 mm typically needs 6; 0.5 mm requires HDI and 8+), set dielectric heights by your impedance targets (e.g., 50 Ω microstrip on FR‑4 with 35 µm Cu uses ~0.18–0.20 mm), and keep every signal adjacent to a continuous plane to limit EMI.

What is a PCB stackup

A stackup is the ordered build of copper and dielectrics from top to bottom (signals, planes, cores, prepregs). Symmetry about the mid‑plane limits bow/twist and helps drill registration. Keeping signal layers directly adjacent to solid reference planes minimizes loop inductance and keeps impedance predictable.

When do you need 4, 6, or 8+ layers

If your densest device is 1.0 mm‑pitch BGA, 4 layers usually suffice when you can route 0.10/0.10 mm (4/4 mil) and dog‑bone to through‑vias outside pads. At 0.8 mm pitch, through‑via fanout generally consumes two inner layers for escape; six layers provides solid planes (L2, L5) and one or two inner signal layers for break‑out and timing control. At 0.5 mm pitch, HDI (0.10–0.125 mm laser microvias, via‑in‑pad, sequential lamination) is the practical path; expect 8+ layers. A fast check: if you cannot complete BGA escape within two signal layers per side without collapsing planes, step up the layer count.

How to pick dielectric heights for 50 Ω and 90 Ω

Use FR‑4 Dk ≈ 3.9–4.3 at ~1 GHz and Df ≈ 0.015–0.02 as planning values, then verify with a 2‑D field solver (IPC‑2141 methods). Typical geometries on FR‑4 are:

• 50 Ω microstrip (outer layer), 35 µm Cu, dielectric height 0.18–0.20 mm: width ≈ 0.28–0.33 mm

• 50 Ω stripline (inner layer), 17 µm Cu, plane‑to‑plane 0.10–0.12 mm: width ≈ 0.20–0.24 mm

• 90–100 Ω differential microstrip at 0.18–0.20 mm height: each width ≈ 0.16–0.20 mm, gap ≈ 0.16–0.22 mm

• 100 Ω differential stripline at 0.10–0.12 mm spacing, 17 µm Cu: each width ≈ 0.11–0.14 mm, intra‑pair gap ≈ 0.12–0.18 mm

Outer‑layer solder mask lowers microstrip impedance slightly; model mask Dk ≈ 3.0–3.5 if present. Keep signal layers immediately adjacent to an unbroken ground plane; avoid plane splits beneath high‑speed routes.

Example 4‑layer FR‑4 stackup

Board thickness 1.60 mm. L1 Signal 35 µm over 0.19 mm prepreg (e.g., 2116 or 2116+1080) to L2 GND 17 µm; core 0.90–1.00 mm to L3 PWR 17 µm; 0.19 mm prepreg to L4 Signal 35 µm. This yields 50 Ω microstrip on L1/L4 with widths ~0.30 mm and supports 90–100 Ω differential pairs with ~0.18 mm width and ~0.18–0.20 mm gap. Keep copper balanced (L1 vs L4) and add thieving where large voids exist.

Example 6‑layer FR‑4 stackup

Board thickness 1.60 mm. L1 Sig 35 µm over 0.18–0.20 mm to L2 GND 17 µm; 0.10–0.12 mm to L3 Sig 17 µm; 0.10–0.12 mm to L4 PWR 17 µm; 0.10–0.12 mm to L5 GND 17 µm; 0.18–0.20 mm to L6 Sig 35 µm. L2 and L5 are solid grounds. With 0.10–0.12 mm around L3/L4, 50 Ω stripline widths fall near 0.22 mm and 100 Ω differential stripline near 0.12–0.14 mm per line with 0.14–0.16 mm gap. Outer‑layer microstrip control remains at ~0.30 mm for 50 Ω with 0.18–0.20 mm dielectric.

Via choices and BGA breakout by pitch

For ≥0.8 mm pitch, through‑hole vias with finished drill 0.20–0.25 mm and pads 0.45–0.50 mm are common; fanout with short dog‑bones to clear two tracks between pads on 1.0 mm pitch at 0.10/0.10 mm rules. At 0.5 mm pitch, use 0.10–0.125 mm laser microvias (1‑n) in pad or short dog‑bones to an adjacent layer; plan sequential lamination for 8+ layers. Stitch ground vias near every layer transition of a high‑speed route; a pair of stitches within 0.5–1.0 mm of the transition shortens the return path. If serial rates are multi‑Gb/s, limit via stubs or backdrill to keep residual stubs below ~0.5 mm.

EMI and crosstalk control with numbers

Route fast pairs as stripline where feasible; if microstrip is required, maintain continuous reference and add via fences along critical edges with spacing ≲ λ/20 in the dielectric. Example: at 2.4 GHz in FR‑4 (effective velocity ≈ c/√4), λ ≈ 75 mm, so fence spacing ≲ 3–4 mm is effective confinement. For near‑end crosstalk on the same layer, keep at least 3× trace‑to‑trace gap (3W rule); for broadside coupling across adjacent signal layers separated by H, offset routing or ensure the interlayer spacing is ≥3H when long parallel runs are unavoidable. Use IPC‑2152 to size power traces for allowed temperature rise when placing them on inner layers.

What to show on a stackup drawing

State concrete targets, not just materials: overall thickness 1.60 ±0.10 mm; finished copper per layer (outer 35 µm, inner 17 µm unless otherwise noted); dielectric targets between each adjacent pair (e.g., L1–L2 = 0.19 mm, L2–L3 = 0.11 mm, L3–L4 = 0.11 mm, L4–L5 = 0.11 mm, L5–L6 = 0.19 mm); allowed prepreg substitutions that preserve thickness (e.g., 2116 ↔ 2×1080); core thickness and glass style family (e.g., 0.96 mm core using 7628); impedance table identifying which layers carry 50 Ω single‑ended and 90/100 Ω differential, with tolerance (±10% typical) and copper thickness assumed; solder mask type and whether it is included in the impedance model. This level of detail lets CAM lock dielectrics that hit your impedances without rework.

Quality and turnaround commitments

ISO 9001:2015 certified quality management system (certificate no. CN‑2023‑Q1156, SGS, valid until June 2027). Quotes returned within 24 hours and DFM feedback within 1 business day. Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria, and RoHS/REACH compliance is supported. For RF and high‑frequency stackups, our partner factory manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies.