What does an HDI PCB mean? Definition, IPC-2226 types, rules

An HDI PCB means a High Density Interconnect printed circuit board that achieves higher routing density by using laser-drilled microvias, fine lines/spacing (about 50–75 µm), and via-in-pad structures, as defined in IPC-2226.

HDI PCB meaning in one sentence

HDI is a build-up PCB technology that adds one or more thin dielectric/copper layers with microvias over a laminated core so dense BGAs and high-speed nets can be escaped in fewer layers and shorter lengths.

How does IPC-2226 define HDI?

IPC-2226 classifies HDI by build-up structure and via types:

• Type I: One build-up layer (BU) of microvias on one or both sides over a core; core has only through-holes (no buried vias).

• Type II: One BU layer on one or both sides over a core that includes buried vias; through-holes may also be present.

• Type III: Two or more BU layers on one or both sides; microvias can be stacked or staggered over buried/through structures.

Skip microvias (outer layer to second BU layer in one laser drill) are recognized where dielectric is thin enough.

Common HDI stackups and via structures

Typical notations are 1+N+1, 2+N+2, etc., where N is the core layer count. Example: a 1+6+1 Type II stack may use blind microvias L1→L2 and L8→L7, buried vias L3↔L6, and plated through-holes from L1→L8 for power and tooling. Via-in-pad is commonly used under 0.5 mm-pitch BGAs to free channels for escape routing.

What are typical HDI design rules?

• Line/space on BU layers: 50–75 µm (2–3 mil); core layers commonly 75–100 µm (3–4 mil).

• Microvia laser drill diameter: 75–125 µm (3–5 mil); capture pad 200–250 µm with ≥50 µm annular ring.

• Microvia depth (dielectric thickness): 50–100 µm per BU layer; aspect ratio ≤1:1.

• Stacking: prefer staggered microvias; if stacked, limit to two levels and specify copper-filled and overplated caps for reliability.

• Via-in-pad: specify conductive (copper) fill for stacked structures; for single-level VIPPO, resin fill and cap plate are common.

• Impedance targets: 50 Ω single-ended microstrip; 85–100 Ω differential stripline/microstrip depending on protocol (e.g., 90 Ω for USB 2.0 HS, ~85 Ω for PCIe/USB 3.x, 100 Ω for Ethernet pairs). Use BU dielectric of ~60–100 µm to meet these with 50–90 µm traces.

• Solder mask dams: ≥75–100 µm between BGA pads to control solder bridging on 0.5 mm pitch.

• Core and BU materials: FR-4 cores with RCC (resin-coated copper) or very thin glass styles (e.g., 2116/1080) for BU; choose Tg and Td consistent with reflow profile and product life.

When should you choose HDI over standard PCB?

• BGA pitch ≤0.5 mm (especially 0.4 mm and below) where dog-bone fanout is no longer feasible.

• High layer-count designs where HDI can reduce total layers by enabling tighter escape and shorter routes.

• High-speed nets that benefit from shorter stubs and better return paths (blind/buried vias reduce via stub length vs. through-holes).

• Space- and weight-constrained products such as smartphones, wearables, compact instrumentation, and small-form-factor networking.

Reliability and manufacturing notes

Microvia reliability depends on copper thickness at the via knee and the thermal cycle profile. Staggered structures distribute strain better than stacked; if stacking is required, specify electrolytic copper fill with cap plating, and avoid stacking more than two levels without qualification. Keep microvia aspect ratio ≤1:1 and ensure adequate capture pad and land reinforcement to mitigate corner cracking. Control via stub length for any through vias on high-speed nets; back-drill if needed. For CAF mitigation, select laminates with suitable glass treatment and resin systems, especially when using very thin dielectrics.

Compliance and inspection options

HyperPCB operates an ISO 9001:2015 certified quality management system (certificate CN-2023-Q1156, SGS, valid until June 2027). Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria, and RoHS/REACH compliance is supported for hazardous substances. Quotes are returned within 24 hours and DFM feedback within 1 business day. Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, and ISO 45001:2018, as well as ISO 13485:2016 and IATF 16949. AEGIS also manufactures its own high-frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies.

Sourcing checklist for engineers

Share stackup intent early (e.g., 1+N+1 vs 2+N+2); specify target impedances and tolerance; call out microvia diameter, dielectric thickness, fill type (resin or copper), stacking vs staggering, and via-in-pad requirements; include any back-drill needs and IPC Class target; attach net list and layer sketches to speed DFM.