What files are required for a 24‑hour PCB assembly quote, and what drives cost?

To receive a PCB assembly price in 24 hours, submit complete build data (BOM, centroid, fabrication and assembly docs), specify standards/tests, and state quantities and sourcing; main cost drivers are placement count and unique MPNs, two‑sided reflow, fine‑pitch/BGA and tiny passives, through‑hole content, test/programming time, and panel utilization.

Exactly which files are needed for a 24‑hour quote?

• BOM: manufacturer name, MPN, reference designator, quantity per assembly, approved alternates (identical form/fit/function), and a DNI list per variant

• Fabrication data: Gerbers (RS‑274X) or ODB++ with stackup note and surface finish (e.g., ENIG, HASL); include key tolerances that affect assembly (board thickness, copper weight)

• Pick‑and‑place/centroid (CSV/XY): refdes, X/Y in mm from a defined PCB origin, rotation 0–359° CCW, and side (top/bottom); keep a consistent 0° definition across parts

• Assembly drawing (PDF): polarity and pin‑1 marks, diode/K marks, keep‑outs, maximum component height by side, and any required hand‑solder operations

• Schematic PDF and/or IPC‑356 netlist for reference and test planning

• Test/programming package: test strategy (flying probe, ICT, AOI, boundary‑scan), limits/procedures, firmware images (HEX/SVF), connectors/cables used

• Panelization drawing: step‑and‑repeat, 5–10 mm rails, three global fiducials per side (1.0 mm copper with ≥2.0 mm soldermask clearance), tooling holes, and depanel method (mouse‑bite, V‑score)

• Special processes: cleaning chemistry (no‑clean vs water‑soluble), conformal coat type (e.g., acrylic/urethane), staking/underfill, and masking map

• Build rules: quantities (e.g., 50/500/2000), variants, delivery batches, sourcing mode (turnkey/consigned/mixed), and target acceptance standard (e.g., IPC‑A‑610 Class 2 or Class 3)

What drives PCB assembly cost?

High placement volume and unique line items set machine and feeder setup time. A design with 1,200 placements and 180 unique MPNs typically costs more to set up than 1,200 placements with 60 unique MPNs, even at the same quantity.

Two‑sided SMT adds a second reflow, extra handling, and potential adhesive or selective rework. Keeping all components on one side removes an entire thermal cycle; if you must place on both, reserve the bottom side for low‑mass passives (0402/0603) and ICs under about 2.0 mm height.

Fine‑pitch and miniatures increase stencil and inspection complexity. Packages at ≤0.5 mm pitch, micro‑BGAs, and 0201/01005 passives push stencil thickness down to 80–100 µm and can require stepped apertures and tighter placement tolerances; BGAs commonly require X‑ray inspection budgeting in most build plans.

Through‑hole content adds wave/selective solder or hand time. Tall or high‑thermal‑mass parts (e.g., large inductors, chassis connectors) may force separate soldering passes; press‑fit or eyelet hardware adds manual operations.

Test and programming add non‑recurring engineering and per‑unit time. Flying‑probe is pad‑access driven and scales with net count; ICT needs a stable netlist and dedicated pads (typical 1.0 mm pad on 2.54 mm grid). In‑system programming often adds 10–120 s per unit depending on interface and image size.

Sourcing and packaging matter. Full reels and trays feed faster than cut tape; equivalent alternates reduce risk and cost. NRND or long‑lead items can introduce expedite fees or broker premiums.

Panel utilization directly affects unit cost. Aim for 70–85% area utilization after rails and fiducials. Example: a 40 × 40 mm board in a 250 × 250 mm panel with 10 mm rails and 2 mm part‑to‑part gaps fits 5 × 5 = 25 units, around 64% utilization; rotating or tightening step‑and‑repeat can raise this into the 70%+ range.

DFM choices that measurably lower price

For single‑pass reflow, keep everything on one side. If two‑sided is unavoidable, limit bottom‑side component height to ≲1.2–1.5 mm and individual mass to ≲0.5 g so parts stay in place without adhesive during top‑side reflow; keep bottom‑side passives at 0603 (1608 metric) or smaller. Use IPC‑7351 land patterns and define the 0° orientation and CCW rotation in your centroid notes to avoid rework.

Match stencil to your mix: 100 µm (4 mil) works for general 0402/0603; use 80–100 µm for dense 0.5 mm‑pitch BGAs/QFNs, and consider step‑up regions (120–150 µm) where large leaded parts need more paste. Avoid via‑in‑pad under BGAs; if you must, specify plated fill and planarization to prevent solder wicking.

Place three global fiducials per side (1.0 mm copper, ≥2.0 mm mask clearance) and local fiducials within ~5 mm of fine‑pitch devices. For test, reserve accessible pads: flying‑probe can hit 0.5–1.0 mm pads with mask clearance; ICT is more robust with 1.0 mm pads on a 2.54 mm grid. Keep at least 5–10 mm panel rails and add tooling holes for stable handling.

Quote timing and quality system

HyperPCB returns quotes within 24 hours and DFM feedback within 1 business day. HyperPCB operates an ISO 9001:2015 certified quality management system (certificate no. CN‑2023‑Q1156, issued by SGS, valid until June 2027).