What HDI PCB design guidelines actually work in fabrication?

Define your HDI level and stackup early

Use a 1+n+1 or 2+n+2 stackup, keep microvias at ≤1:1 aspect ratio (75–125 µm laser drills), prefer staggered over stacked microvias, and specify copper‑filled via‑in‑pad for 0.4 mm BGAs.

What microvia sizes and aspect ratios work?

For L1–L2 and Ln–(n−1) microvias, target 75–100 µm drill with ≤100 µm dielectric so depth/diameter ≤1:1. Use 200–250 µm capture pads with ≥50 µm radial annular ring. Control registration; budget ±25–35 µm layer-to-layer. For stacked structures, plate-fill lower microvias before stacking and limit stacks to two high; staggered microvias are more tolerant to thermomechanical stress.

Via‑in‑pad or dogbone fanout?

• 0.40 mm pitch BGAs: require VIPPO (copper‑filled and capped) to prevent solder wicking; call out IPC‑4761 Type VII. Specify fill voids <5% and cap plating 15–25 µm.

• 0.50 mm pitch BGAs: dogbone fanout can work with 50/50–75/75 µm trace/space and 200–250 µm microvia pads. Keep solder mask dams ≥75–100 µm; use mask‑defined pads if needed.

Impedance control and dielectric choices

Plan impedance with the stackup, not after routing. Typical HDI pairs use 50 Ω single‑ended and 90 Ω differential. For FR‑4 (Dk ≈3.6–3.9) with 18 µm foil, 50 Ω microstrip often lands near 90–110 µm width over 80–100 µm dielectric; stripline 50 Ω can be ≈90–120 µm width in 80–100 µm dielectrics between planes. Validate with your fabricator’s field solver per IPC‑2221/2226; use test coupons per IPC‑6012.

Staggered or stacked microvias?

Prefer staggered. If you must stack, keep to two‑high maximum, ensure the lower microvia is fully copper‑filled and planarized before drilling the upper, and maintain tight capture pads. For staggered, offset at least 75–100 µm to absorb registration and reduce local copper density spikes.

Copper, spacing, current, and loss

Use 12–18 µm outer copper where fine routing is dense; heavy copper rapidly forces wider lines, higher etch bias, and worse impedance tolerance. For current, reference IPC‑2152 and derate in HDI: long 50 µm traces heat quickly—split current paths or move to planes. Maintain at least 3W spacing from high‑speed lines to other conductors to control crosstalk; keep return‑via fences near layer transitions.

Reliability traps to avoid

Avoid glass‑stop microvias: align microvia landings to resin‑rich areas (spread‑glass styles like 1080/2116 or low‑weave options reduce risk). Balance copper by quadrant to limit warp. If through‑holes coexist with high‑speed channels, backdrill to keep stubs <300 µm for multi‑Gbps links. Call out IST/microsection acceptance aligned to IPC‑6012 for stacked‑via builds.

Fabrication notes that prevent surprises

Specify: IPC‑4761 via types (e.g., Type VII for VIPPO), target dielectric thicknesses per pair, maximum sequential lamination cycles, filled‑via requirements (density, hardness), backdrill limits, impedance targets and tolerances, AOI/X-ray on microvias, and solder mask dam minima. Include keep‑outs: microvia‑to‑copper ≥100 µm, copper‑to‑board edge ≥300 µm.

Quick HDI rules of thumb

• Define 1+n+1 for 0.4–0.5 mm BGAs; move to 2+n+2 only when fanout forces it

• Laser drill 75–100 µm; dielectric 60–100 µm; keep aspect ratio ≤1:1

• Capture pads 200–250 µm; annular ring ≥50 µm radial (more for stacked)

• VIPPO for 0.40 mm; dogbone acceptable for 0.50 mm with 50/50–75/75 µm

• Limit stacked microvias to two‑high; prefer staggered with 75–100 µm offset

• Outer copper 12–18 µm in dense HDI; avoid >35 µm on fine‑line layers

• Impedance: 50 Ω SE, 90 Ω diff typical; validate with fabricator coupons

• Backdrill through‑hole stubs to <300 µm near high‑speed channels

• Solder mask dams ≥75–100 µm; consider mask‑defined pads for fine pitch

How to tie guidelines to IPC standards?

Use IPC‑2226 for HDI design practices, IPC‑4761 for via structures, IPC‑6012 for qualification/acceptance, and IPC‑2152 for current and thermal modeling. Document which clauses govern acceptance on your drawing to avoid ambiguity at CAM.

How we support HDI builds

We operate an ISO 9001:2015 certified QMS (certificate CN‑2023‑Q1156, SGS, valid to June 2027). Boards can be built and inspected to IPC Class 2 or Class 3 acceptance criteria, and RoHS/REACH compliance is supported. Quotes are returned within 24 hours and DFM feedback within 1 business day. Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, and ISO 45001:2018 management systems, plus ISO 13485:2016 and IATF 16949 for regulated sectors. Engage us early with your intended stackup, impedance table, and via types so DFM aligns with these HDI guidelines.