What impedance for MDI traces between RJ45 and magnetics?

Use 100 Ω differential impedance for the MDI traces between the RJ45 jack and the Ethernet magnetics.

Target impedance and tolerance

IEEE 802.3 twisted‑pair Ethernet is defined around a 100 Ω differential channel. Route the RJ45–magnetics segment as 100 Ω differential, with a fabrication tolerance of ±10% and system tolerance within ±15% to align with 802.3 return‑loss expectations.

Why 100 Ω between the RJ45 and the magnetics?

That short segment sits on the cable side of the isolation transformer. It interfaces electrically to the 100 Ω cable through the magnetics and any common‑mode choke in the connector. Matching this segment to 100 Ω minimizes mode conversion and radiated emissions around the connector where fields are strongest.

How short and how symmetrical should the pair be?

Keep this segment as short as placement allows—ideally under 20–25 mm. Maintain tight coupling and length‑match within a pair to ≤50 mil (≈1.27 mm). Avoid plane splits under the pair, keep a continuous reference, and do not add series capacitors or stubs on the cable side (PoE requires DC continuity).

Stackup examples that hit 100 Ω differential

Use a field solver for your exact laminate and mask. The values below are typical starting points that many shops can build; verify with your fabricator.

• 4‑layer, microstrip (L1 over L2 GND), FR‑4 (Er≈3.9), soldermask present, 35 µm Cu, h=0.10 mm: W≈0.18 mm, S≈0.15–0.18 mm → ~100 Ω diff

• 4‑layer, microstrip (L1 over L2 GND), FR‑4 (Er≈3.9), soldermask present, 35 µm Cu, h=0.18 mm: W≈0.32–0.36 mm, S≈0.22–0.30 mm → ~100 Ω diff

• 6‑layer, symmetrical stripline (L3 between L2/L4 planes), FR‑4 (Er≈4.0), 35 µm Cu, H(top/bot)=0.20 mm: W≈0.22–0.26 mm, S≈0.20–0.26 mm → ~100 Ω diff

Notes: 7628 glass styles raise effective Dk (lowering Z0). Soldermask lowers Z0 by ~2–4%; include it in the model. If your fab guarantees ±10% differential, center your target at 100 Ω.

Routing details that reduce EMI near the jack

• Keep the pair tightly coupled up to the connector pins; don’t flare the spacing at the footprint.

• Use paired vias and identical antipads if layer transitions are unavoidable; minimize via stubs.

• Maintain at least 3× the dielectric height clearance to other aggressors; avoid parallelism with noisy clocks.

• Reference the pair to chassis/earth near the jack per your EMC plan; do not reference to a split plane along the run.

What if my RJ45 has integrated magnetics?

Treat the short PCB segment from the connector pins to the common‑mode choke/transformer pins the same way: 100 Ω differential, very short, and tightly coupled. The connector’s internal wiring does not remove the need for controlled impedance on the PCB.

Verification and fabrication notes

• Specify 100 Ω differential controlled impedance on the fab drawing and call out the test method (TDR) and tolerance (±10%).

• Provide the stackup (dielectric thicknesses, resin systems, copper weights) and allow the fabricator to fine‑tune W/S.

• If you must cross a reference split, add a stitching capacitor path at both lines of the pair, but redesign to avoid the split if possible.

• Accept boards to IPC‑6012 with the product class that matches your reliability target; Class 2 is common for networking, Class 3 for high‑reliability builds.

Manufacturing assurance at HyperPCB

• ISO 9001:2015 certified QMS (SGS CN-2023-Q1156, valid to Jun 2027)

• Quotes in 24 hours and DFM feedback within 1 business day

• Boards buildable and inspectable to IPC Class 2 or Class 3

• RoHS and REACH compliance supported

• Partner factory AEGIS: ISO 9001/14001/45001 systems

• AEGIS also maintains ISO 13485 and IATF 16949

• Partner factory manufactures high‑frequency laminates and supplies RF PCB fabricators in China

Quick checklist

• Target 100 Ω differential, ±10% fab tolerance

• Length‑match within a pair ≤50 mil; keep total length ≤25 mm if possible

• Continuous reference plane; avoid splits and stubs

• Tight coupling up to the connector pins; minimize via count

• Confirm dimensions with a 2D field solver and your fabricator