What is a good 4-layer PCB stackup for impedance and EMI?

Use a symmetric 4-layer with L1/L4 signals, L2 solid ground, L3 power plus secondary routing, with 0.09–0.18 mm dielectric to the planes and ~1.6 mm overall thickness.

Recommended 4-layer PCB stackup

• Standard 1.6 mm FR-4 (Dk ~3.7–4.1): L1 1 oz signal / 0.18 mm prepreg / L2 1 oz GND / 1.0 mm core / L3 1 oz PWR+signal / 0.18 mm prepreg / L4 1 oz signal. Typical 50 Ω microstrip on L1 requires ~12–14 mil width (35 µm Cu). 100 Ω diff pair ≈ 9–11 mil width, 9–12 mil gap (verify with a field solver).

• High‑speed 1.6 mm FR-4: L1 0.5 oz signal / 0.09–0.10 mm prepreg / L2 1 oz GND / 1.3–1.4 mm core / L3 1 oz PWR+signal / 0.09–0.10 mm prepreg / L4 0.5 oz signal. With 0.09–0.10 mm dielectric, 50 Ω microstrip is typically ~6–8 mil; 100 Ω diff ~5–6 mil width with ~6–8 mil gap (solver required). Keep the stack symmetric to control warp.

Which dielectric and copper weights should I pick?

Thin dielectrics (0.09–0.13 mm) let you hit 50 Ω with ~5–8 mil traces; thicker (0.15–0.20 mm) pushes widths to ~10–16 mil. Use 0.5 oz on outer signal layers for finer etching and lower roughness loss; 1 oz on planes reduces IR drop. Select glass styles accordingly: 1080/2116 pairs yield ~0.10–0.12 mm; 2116/7628 pairs yield ~0.16–0.20 mm after press. Always request the fabricator’s press-out data and Dk/Df at your frequency.

Example impedance targets and widths

• Single‑ended 50 Ω microstrip on L1: ~6–8 mil (h ≈ 0.10 mm, 0.5 oz), ~12–14 mil (h ≈ 0.18 mm, 1 oz).

• Differential pairs: 85–100 Ω are common (PCIe 85 Ω, Ethernet 100 Ω, USB HS 90 Ω). Expect ~5–6 mil traces and ~6–10 mil gaps with 0.09–0.10 mm dielectrics on outer layers. For inner striplines (to L2/L3), widths are smaller for the same impedance due to dual‑plane coupling—use a solver (e.g., Polar, Saturn) and specify tolerance (±10% typical).

How to control EMI on 4 layers?

Make L2 a continuous, unsplit ground; route high‑speed on L1 over that plane. Keep power splits on L3; never route over plane gaps. Place stitching vias at every plane split edge and near any signal via transitions (within ~1–2 mm) to provide a short return path. Avoid copper thieving or voids beneath fast edges. Keep high‑dv/dt nets short and reference one plane consistently.

Via transitions, stitching, and plane splits

When a signal switches between L1 and L4, add a nearby ground via to tie L2/L3 reference paths. Keep via stubs short; choose through‑holes sized for your pitch and frequency budget, and avoid routing fast pairs through long unused barrels. If you must cross a power split, add a capacitor bridge or reroute to maintain return continuity.

Do I need controlled impedance on inner layers?

If any critical nets must be shielded from surface noise or require tighter coupling, you can route as striplines to L2/L3. Expect smaller widths than surface microstrips for the same Z0 and higher loss due to dielectric. Provide a target stackup with exact press‑out thicknesses and copper weights; tolerance of ±10% for Z0 is common. Reference IPC‑2221 for design and IPC‑6012 for qualification/performance.

What to include in your fab stackup note?

Call out layer order, copper weights, target dielectrics (press‑out, not nominal), Dk/Df at your operating frequency, controlled‑impedance nets with targets and tolerance, and test coupon requirements. Include allowed material sets (e.g., FR‑4 mid‑loss vs low‑loss) if your timing/attenuation budget depends on it.

Compliance and turnaround at HyperPCB

HyperPCB operates an ISO 9001:2015 certified quality management system (certificate CN-2023-Q1156, SGS, valid to June 2027). Boards can be built and inspected to IPC Class 2 or Class 3 acceptance criteria, and RoHS/REACH compliance is supported. We return quotes within 24 hours and DFM feedback within 1 business day.