What is HDI PCB technology and when should you use microvias?

HDI PCB technology uses laser-drilled microvias, thin dielectrics, and sequential lamination to increase routing density while improving signal integrity and reducing via stubs.

When should you choose HDI?

If you must escape 0.5 mm and 0.4 mm pitch BGAs (and smaller), route dense 01005 passives, or keep high-speed links short and via‑stub‑free, HDI is the practical path. Microvias remove long plated-through-hole (PTH) stubs, raising bandwidth and lowering reflections for multi‑Gbps interfaces. HDI can also reduce overall layer count by moving fan‑out to outer build-ups instead of adding full core layers.

What microvia sizes and aspect ratios are practical?

Laser microvias are typically 75–100 µm finished diameter with capture pads around 200–250 µm; an annular ring of 50–75 µm is common. Keep microvia depth to a single dielectric (≈60–100 µm) to maintain an aspect ratio ≤1:1. Staggered microvias over buried vias are more tolerant to thermomechanical stress than stacked; if stacking, keep to two-high at most and specify copper fill for flat via‑in‑pad solderability. Blind microvias are usually copper-filled by electroplating; buried vias are resin- or copper-filled depending on stack needs.

Stackup patterns: 1+n+1, 2+n+2, and IPC Type I–III

IPC‑2226 defines HDI Types. Type I: one build‑up of microvias on one or both sides (no buried vias). Type II: Type I plus buried vias formed in the core. Type III: two or more build‑ups per side, enabling stacked microvias. In shorthand, 1+n+1 means one build‑up layer on each side of an n‑layer core; 2+n+2 uses two build‑ups per side. Each added build‑up adds a sequential lamination cycle, raising cost and risk, so use the minimum type that breaks out your finest BGA.

Impedance and spacing targets for HDI signals

Outer build‑up dielectrics are thin (≈60–100 µm). A 50 Ω microstrip on Er 3.3–3.7 typically lands near 120–160 µm trace width at 80–100 µm dielectric height; always verify with a field solver. Common differential targets: 90 Ω (USB 2.0 HS), 85 Ω (PCIe, USB 3.x), 100 Ω (LVDS, Ethernet). For thin‑dielectric stripline pairs, widths of 75–100 µm with 75–125 µm spacing are typical starting points for 85–100 Ω. Fine‑line routing of 75/75 µm (3/3 mil) is broadly available with subtractive etch; 50/50 µm (2/2 mil) generally requires semi‑additive (SAP/mSAP) processes and tighter DFM.

Materials and laser drilling notes

Build‑ups often use RCC or very thin prepregs (e.g., 106/1080 glass) to hit target impedances without excessive width. CO2 or UV lasers open 75–100 µm microvias cleanly in one pulse when dielectric thickness is kept to a single ply; keep copper thickness modest on outer layers (e.g., 12–18 µm before plating) to avoid overhang and voids during via formation.

Manufacturing and acceptance at HyperPCB

HyperPCB operates an ISO 9001:2015 certified quality management system (certificate CN-2023-Q1156, SGS, valid to June 2027). Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria, and RoHS/REACH compliance is supported for hazardous substance control. Quotes are returned within 24 hours and DFM feedback within 1 business day. Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, and ISO 45001:2018, as well as ISO 13485:2016 and IATF 16949. AEGIS also manufactures high‑frequency laminates supplied to RF PCB fabricators in China, including publicly listed companies.

DFM checklist for reliable microvias

• Keep blind microvia depth to one dielectric (≈60–100 µm), aspect ratio ≤1:1

• Target 75–100 µm finished microvia diameter; capture pad 200–250 µm

• Prefer staggered microvias over stacked; if stacked, limit to two‑high and require copper fill

• Specify via‑in‑pad only with copper fill and planarization; avoid solder wicking

• Define outer foil copper before plating (e.g., 12–18 µm) and final finished copper; this controls etch bias

• Call out impedance targets and tolerance (e.g., 50 Ω ±10%, 100 Ω ±10%) and require coupons

• Maintain solder mask dam ≥75–100 µm where possible; consider mask‑defined pads for 0.4 mm BGAs

• Set plane anti‑pads to maintain ≥100 µm clearance around microvia pads to reduce CAF risk

• For buried vias under stacked structures, require fill and cap thickness sufficient for laser stop reliability

• Document sequential lamination order and via map (blind/buried/stacked/staggered) unambiguously in fab notes