What is impedance in PCB? Practical rules, targets, and stackup choices

What is impedance in a PCB?

Impedance on a PCB is the characteristic impedance (Z0) of a trace acting as a transmission line with its return path. It is set by geometry and materials, not just by the IC. For single‑ended lines you usually target about 50 Ω; for differential pairs, typical targets are 85–100 Ω depending on the interface.

Why does controlled impedance matter?

When the trace Z0 mismatches the driver/receiver, edges reflect. That causes eye‑diagram closure, EMC issues, and timing errors. Above about one‑tenth of a signal’s rise‑time length (for example, a 200 ps edge reaches ~30 mm on FR‑4), treat the trace as a transmission line and design for a target impedance with a stated tolerance, commonly ±10%.

Microstrip vs stripline — what changes?

A microstrip is on an outer layer over a reference plane; its fields fringe into air and dielectric, so Z0 is lower when you add solder mask and higher when mask is removed. A stripline is buried between planes; all fields are in the dielectric, so it is more uniform and less radiative but needs narrower lines to reach the same Z0.

Typical targets by interface

• Single‑ended RF, clocks: 50 Ω

• USB 2.0 D+/D− differential: 90 Ω ±10%

• USB 3.x, PCIe, SATA differential: 85 Ω ±10%

• Ethernet (100/1000BASE‑T) differential: 100 Ω ±10%

Always confirm the spec revision you are designing to.

What variables change impedance?

Key variables are dielectric thickness to the reference plane (h), trace width (w), copper thickness (t), dielectric constant (εr), spacing (s) for differential pairs, and copper roughness. Solder mask over a microstrip typically lowers Z0 by ~1–3 Ω. Thicker copper (for example 1 oz ≈ 35 µm vs 0.5 oz ≈ 17 µm) and tighter coupling in a pair both lower impedance. Weave choice and resin content matter: 7628 prepreg is thick (~0.18–0.20 mm per ply) with a coarse weave; 2116 (~0.10 mm) and 1080 (~0.07 mm) are thinner and help reach higher Z0 with manufacturable widths.

How do you calculate or model it?

Closed‑form equations like IPC‑2141 are good for estimates. For a microstrip, a common approximation is Z0 ≈ 60/√(εeff) · ln(8h/(w + t)). Use a 2D field solver for accuracy, especially for differential pairs and when solder mask or roughness are significant. FR‑4 εr is typically ~3.7–4.2 at 1 GHz; the effective εeff for microstrips is lower because part of the field is in air.

How do differential pairs behave?

Differential impedance Zdiff is roughly 2× the odd‑mode impedance; tighter spacing (smaller s) increases coupling and reduces Zdiff. To keep coupling consistent, maintain uniform spacing, identical reference planes, and minimal skew (match lengths and avoid unmatched stubs). Neckdowns at BGA breakouts temporarily raise Zdiff; keep them short.

What should I put on the fab drawing?

• Identify each controlled structure: layer(s), single‑ended or differential, microstrip/stripline

• State the target impedance(s) and tolerance (for example 50 Ω ±10%, 100 Ω diff ±10%)

• Specify the reference plane(s), intended stackup (core/prepreg types, ply counts), and copper weights

• For differential pairs, give trace width and spacing intent or allow the fabricator to tune width/spacing to meet target

• Call out test method (for example TDR per IPC‑TM‑650 2.5.5.7) and test coupon style

• Note whether solder mask covers controlled traces and the surface finish used (OSP, ENIG, etc.)

How is impedance verified in fabrication?

Manufacturers build test coupons with the same stackup and geometry, then measure with time‑domain reflectometry (TDR). Results are compared against your target and tolerance. Acceptance is usually tied to performance standards such as IPC‑6012; make sure your drawing references the required class and test frequency or rise‑time where relevant.

A practical stackup note

On a 4‑layer board, using inner‑layer striplines helps EMI. To reach 100 Ω differential with 0.5 oz inner copper and a plane‑to‑signal dielectric of ~0.10 mm (a 2116 ply), expect narrow lines and moderate pair spacing. If outer‑layer routing is required, remember that adding solder mask may drop a 50 Ω microstrip by ~1–3 Ω; compensate in width or remove mask locally.

About build standards and compliance

Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. An ISO 9001:2015 certified quality management system is maintained (certificate no. CN-2023-Q1156, issued by SGS, valid until June 2027). RoHS and REACH compliance is supported for hazardous substance control.