What is PCB prototype manufacturing and how do you prepare for it?

PCB prototype manufacturing is short‑run fabrication of your production‑intent PCB to validate stackup, impedance, assembly, and test before committing to volume; preparation means releasing complete manufacturing data, locking a stackup, and applying DFM rules you can measure.

What is PCB prototype manufacturing

A prototype is typically a small lot (often 5–20 pcs) built to the same design rules you’ll use in production, with options like controlled impedance, specific finishes (ENIG, lead‑free HASL, immersion tin), flying‑probe electrical test, and IPC Class 2 or Class 3 acceptance criteria. Use it to prove signal integrity, fit, thermal paths, and assembly yields on critical packages (e.g., 0.5 mm‑pitch BGAs).

Which files do I need to release?

• Fabrication data: Gerber X2 or ODB++ (preferred), copper for all layers, solder mask, silkscreen, paste, board outline, impedance table

• Drill data: Excellon with plated/non‑plated separation, tool list, drill map; finished hole sizes and tolerances (typical ±0.075 mm PTH, ±0.10 mm NPTH)

• Netlist: IPC‑D‑356 to enable electrical test correlation

• Stackup: total thickness (e.g., 1.6 mm), copper weights (e.g., 1 oz outer, 0.5 oz inner), dielectric types (e.g., FR‑4, 7628/2116/1080), target Er/Dk if controlled impedance

• Fab drawing: IPC class (2 or 3), outline tolerance (e.g., ±0.10 mm routed), copper‑to‑edge (≥0.25 mm), mask expansion (2–4 mil), finish, peelable masks/score/rout notes

• Assembly data (if needed): centroid/XY, BOM with exact part numbers, panelization/pallet details, test points and access, reflow profile guidance

Stackup and materials for the first article

For general digital designs, a 4‑layer (L1‑sig/L2‑GND/L3‑PWR/L4‑sig) at 1.6 mm with 1 oz outer and 0.5 oz inner is a practical baseline. Common dielectrics include 7628 cores and 2116/1080 prepregs (FR‑4 Dk ≈ 3.8–4.3 at 1 GHz). If you need tighter impedance or lower loss, move high‑speed pairs to stripline (between planes) or select low‑loss materials (e.g., PTFE, hydrocarbon‑ceramic). Keep dielectric to the nearest plane small (≈0.10–0.18 mm) for outer‑layer microstrips.

What DFM rules avoid scrap?

Stay inside conservative, measurable limits on your first spin: trace/space ≥ 4/4 mil (3/3 mil only if necessary), finished PTH ≥ 0.25–0.30 mm with aspect ratio ≤ 10:1, annular ring ≥ 4 mil (Class 2) or 5–6 mil (Class 3), solder mask dam ≥ 4 mil, copper‑to‑rout ≥ 10 mil (≥ 15 mil if V‑score), silkscreen‑to‑pad ≥ 5 mil, copper‑to‑NPTH ≥ 0.25 mm. Use thermal reliefs on plane connections; avoid via‑in‑pad unless filled/capped for ≤ 0.5 mm‑pitch BGAs. Define controlled depth for countersinks/counterbores and keep copper clearances from mechanicals ≥ 0.5 mm.

Impedance control basics for prototypes

Call out targets and tolerances on the fab drawing and include an impedance table. Typical values: 50 Ω single‑ended microstrip; 90 Ω differential for USB 2.0 HS; 85 Ω differential for PCIe; 100 Ω differential for Ethernet/HDMI. On FR‑4 with outer‑layer H ≈ 0.10 mm to plane and 1 oz copper, 50 Ω microstrip often lands around 0.18–0.23 mm (7–9 mil) width; 90 Ω differential pairs often use W ≈ 0.13–0.17 mm with S ≈ 0.13–0.20 mm. Inner‑layer striplines with H ≈ 0.10 mm and 0.5 oz copper commonly yield 100 Ω differential at W ≈ 0.10–0.12 mm and S ≈ 0.12–0.18 mm. Use a field solver (per IPC‑2141/IPC‑TM‑650 methods) and request test coupons; ±10% impedance tolerance is typical in prototype builds.

How fast can a prototype be built?

Industry‑wide, simple 2‑layer FR‑4 can be expedited in 1–3 working days and 3–5 days standard; 4–6 layers typically run 3–7 days. Add time for controlled impedance, fine lines (≤ 3/3 mil), filled vias, or specialty laminates. Assembly adds stencil procurement and placement/test time.

Quality, compliance, and RF options

We operate an ISO 9001:2015 certified quality management system (certificate CN‑2023‑Q1156, issued by SGS, valid until June 2027). Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH compliance is supported for hazardous substance control. For regulated programs, our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, and ISO 45001:2018, plus ISO 13485:2016 (medical) and IATF 16949 (automotive). For RF work, our partner factory manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies.

What happens after you send files?

Expect a fast manufacturability loop: we return quotes within 24 hours and provide DFM feedback within 1 business day so you can approve stackup, impedance, and critical tolerances before the first article proceeds.