What to include in a PCB assembly drawing? Checklist, symbols, files

A PCB assembly drawing tells the assembler exactly how to place, orient, solder, inspect, and test every component on your board.

What is a PCB assembly drawing?

It is the controlled manufacturing document for populated boards: it ties the BOM, centroid (XYRS), and process notes to unambiguous visuals of top and bottom sides so placement, soldering, AOI/ICT, and functional test can be executed the same way by every line and shift.

Minimum content checklist

• Top and bottom assembly views with reference designators; callouts for polarity (pin‑1, +/−, A/K), mechanical keepouts, height limits; DNP list; variant table; fiducials and tooling holes; panelization and break‑off method (V‑score or tab‑route); coordinate units and origin; test access map; process notes (stencil thickness, paste alloy, reflow profile, wave/hand ops); cleaning/coating requirements; acceptance class and workmanship standard; ESD/Moisture handling; packaging and labeling requirements; drawing number, rev, and change history.

Which views and symbols are required?

Provide at least: 1) top assembly view with component outlines and refdes, 2) bottom assembly view mirrored correctly, 3) detail views for dense areas, 4) panel drawing if delivered in array form. Use clear symbols: pin‑1 dot or chamfer on ICs; anode bar for tantalum caps; diode cathode bar; connector key notch. Keep symbol legend on the sheet.

How do I call orientation and polarity?

State your rotation convention in text and match your centroid: e.g., rotations measured CCW from 0 deg; 0 deg equals text‑readable on top side. Mark pin‑1 triangles on both silkscreen and copper for fine‑pitch ICs; add a note such as “All polarized parts oriented as shown; polarity governs if CAD and silkscreen disagree.” For LEDs/diodes, show A/K on the outline and tie it to schematic net names.

Reflow and wave process notes that matter

For lead‑free SAC305, give a numeric profile window: ramp 1.0–3.0 degC/s; soak 150–180 degC for 60–120 s; time above 217 degC 45–90 s; peak 240–250 degC, 30–60 s within 5 degC of peak. Stencil: 100 µm (4 mil) for 0402/0.5 mm pitch; 120 µm (5 mil) for 0603/0.8 mm pitch; 10–20% aperture reduction on fine‑pitch pads; home‑plate on large thermal pads with 50–70% coverage and 0.3–0.5 mm windowed mask. If wave soldering, specify lead‑trimming, selective‑wave pallets, and glue points if required; pot 250–260 degC, contact 2–4 s, topside preheat 100–130 degC.

Fiducials, panelization, and tooling for pick‑and‑place

Global fiducials: three per panel, 1.0 mm bare copper with 2.0–3.0 mm soldermask clearance; place near panel corners, asymmetrically. Local fiducials: two near fine‑pitch parts (<0.5 mm). Panel rails: 5–10 mm on two opposite sides with three tooling holes (3.0 ±0.05 mm NPTH) and at least two global fiducials on each rail. Note break‑off: V‑score 0.4–0.5 mm web, 30 deg; or tab‑route with 1.0–1.5 mm tabs and mouse‑bites (0.5–0.8 mm drills, 0.5–1.0 mm pitch). State board origin and array origin.

Test access, AOI, and acceptance classes

Call out test pads: 1.0 mm min bare copper pads on 2.54 mm grid where possible; no soldermask on pads; 1.5 mm keepout around each. Label nets or provide a test map table. Reserve AOI clearance: 1.0 mm around refdes and polarity marks; ensure marks are not hidden under parts. Specify workmanship: IPC‑A‑610 Class 2 or Class 3 and J‑STD‑001 for soldering; note conformal‑coat keepouts if applicable. If you require RoHS/REACH, state it on the drawing.

How do I document variants and DNP options?

Include a variant table listing refdes, MPN, and population state per variant. Keep a single master drawing with clearly bounded sections for options (e.g., R123/R124 stuffing for 3V3/5V0). Avoid free‑text notes—use a structured table that your ERP can parse.

What files do I send with the drawing?

Release as PDF plus native CAD (for ECAD: ODB++ or IPC‑2581; or Gerber X2 + assembly drawings). Include BOM with approved MPNs and alternates, centroid (XYRS) with units and rotation convention, reflow profile, and panel file. If moisture‑sensitive parts are present, include J‑STD‑033 handling and J‑STD‑020 reflow classification in notes.

Quick mistakes to avoid before release

• Refdes mismatches between drawing and BOM (run a scripted check).

• Missing origin/units causing 90/180 deg rotations on line.

• Polarity only on silkscreen under a body—duplicate on copper/assembly layer.

• No global/local fiducials for 0.5 mm pitch and smaller.

• DNP parts left in centroid—remove or mark do‑not‑place in file and on drawing.

What will HyperPCB do with your drawing?

We operate under an ISO 9001:2015 certified quality management system (certificate CN‑2023‑Q1156, SGS, valid to June 2027). We return quotes within 24 hours and DFM feedback within 1 business day, helping you catch issues like ambiguous polarity or insufficient fiducials early. Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria, and RoHS and REACH compliance is supported when you call it out in your documents.

Reference standards to cite on the drawing

IPC‑A‑610 (acceptability), J‑STD‑001 (soldering), IPC‑7351 (land patterns, orientation conventions), IPC‑2615 (PBA documentation), J‑STD‑020/033 (MSL/reflow), and ANSI/ESD S20.20 (ESD controls).