Which IPC‑7351 density level in Altium gives the best DFA and yield?

For 0.5–0.8 mm pitch parts on a 100–125 µm stencil, select IPC‑7351 Density Level B; use Level C for 0.4–0.5 mm BGAs and 0201/01005 on 80–100 µm stencils; use Level A for wave‑soldered SMDs, heavy components, or hand‑rework builds.

What do IPC‑7351 A/B/C change?

A/B/C scale land dimensions, courtyard excess, and the paste aperture starting point in Altium’s IPC‑Compliant Footprint Wizard. Larger A pads increase toe/heel allowances and placement margin; smaller C pads trade margin for area. For gull‑wing leads, practical land goals that map well to A/B/C selections are: toe 0.25–0.50 mm, heel 0.20–0.40 mm, and side 0.05–0.20 mm per side, tuned by pitch and rework needs.

Quick numeric picks by package family

• Chip passives (0402–1206): Level B with 100–125 µm stencil; keep courtyard excess ≈0.2–0.25 mm/side. For 0201/01005, Level C can cut solder volume and tombstoning with 80–100 µm stencils and tight placement.

• Gull‑wing (SOIC/TSSOP/QFP, 0.5–0.8 mm pitch): Level B for reflow lines; Level A when ≥0.8 mm pitch, wave‑solder, or frequent hand rework. Target toe 0.25–0.50 mm, heel 0.20–0.40 mm, side 0.05–0.20 mm.

• QFN/DFN: Level B with NSMD perimeter pads; window the center‑pad paste to 50–70% coverage to limit float/voids. Consider Level C only when keep‑outs are extremely tight.

• BGA: Level B with NSMD pads is common. As a start, land diameter ≈0.8–0.9× ball diameter (e.g., 0.25 mm pad for a 0.30 mm ball), solder mask expansion 60–80 µm per side. Move to Level C at 0.4–0.5 mm pitch if bridging shows up in print tests.

Courtyard, solder mask and stencil numbers

For most passives and QFN perimeters, 0.2–0.25 mm courtyard excess per side eases placement and AOI; tall or gull‑wing parts benefit from 0.25–0.5 mm. Use NSMD on fine‑pitch; typical mask expansion is 60–100 µm per side on FR‑4, and keep mask web ≥75–100 µm between pads to avoid breakout. Use a 125 µm stencil for general SMT and 100 µm for ≤0.5 mm pitch; keep aperture area ratio ≥0.66 and trim apertures by 0–10% where print‑test bridging appears. Keep silkscreen ≥0.15–0.20 mm from exposed copper to prevent ink on pads.

When should I override the Altium Wizard?

If the supplier datasheet’s terminal sizes or tolerances differ from the nominal body code, enter the measured values and re‑derive the land pattern. At very fine pitch or for ultra‑small passives, Level C plus tuned paste apertures (after print trials) often reduces bridging and tombstoning. For wave‑soldered SMD or heavy parts, choose Level A, increase toe fillet, and add chip‑stoppers or thieving as needed. On rework‑intensive builds, Level A improves hand access; document the chosen density (e.g., suffix _B) so layout and assembly teams see the intent.

DFM and acceptance at HyperPCB

We return quotes within 24 hours and DFM feedback within 1 business day. Builds can be manufactured and inspected to IPC Class 2 or IPC Class 3 acceptance criteria. RoHS and REACH substance control is supported. Our quality management system is ISO 9001:2015 certified (SGS certificate CN‑2023‑Q1156, valid until June 2027).