Which PCB assembly machine fits your mix? Use real CPH, accuracy, and profile math

If your builds are ≤0.5 mm pitch and each lot is under ~20k placements, a single flexible placer delivering ~8–15k real CPH with a 7–9‑zone reflow oven is sufficient; 01005/0.4 mm pitch or >20k placements per lot typically needs a chip‑shooter + flexible placer and inline SPI/AOI to hold takt.

Real CPH and takt time: how to compute?

Rated CPH is optimistic. Use line math: Takt (s/board) is the maximum of print time, place time, reflow throughput per board, and AOI time. Boards/hour = 3600 ÷ Takt. Real CPH ≈ Boards/hour × placements/board. Example: 360 placements/board; printer 18 s; placement 48 s; reflow conveyorized at 0.85 m/min yields 32 s/board; AOI 20 s. Takt = 48 s → 75 boards/hour → real CPH ≈ 27,000. If your catalog PnP is 50k CPH, a derate of ~50–60% is typical for high‑mix, so 25–30k real is plausible and correctly sized with margin.

Accuracy vs package pitch and part size?

Look for 3σ repeatability. ±50 μm @ 3σ is workable for 0.5 mm pitch QFN/BGA with controlled paste; ±30 μm is a safer target for 0.4 mm pitch CSP/μBGA and 01005 (0.4 × 0.2 mm) chips. Ensure vision supports on‑the‑fly centering and BGA ball recognition. Check component range (01005 up to ~45 × 45 mm; heights to ~15 mm), board size (~510 × 460 mm class), and feeder capacity versus your unique part count.

Printing and SPI set the defect floor

Most SMT defects originate at the stencil. Use IPC‑7525 style rules: area ratio ≥ 0.66; 100–130 μm foils for 0.5 mm pitch; 80–100 μm for 0.4 mm. Start 1:1 to 1:1.05 aperture‑to‑pad for fine‑pitch; radius QFN corners; use home‑plate/diamond features on thermal pads to control voiding. SPI should control paste volume/height with process targets like Cpk ≥ 1.33 on critical footprints and drive automatic printer offsets/wipe cycles.

Reflow numbers that choose the oven

For SAC305, profile to ~1–3 °C/s ramp, 45–75 s above 217 °C, peak 240–250 °C, and ≤3 °C/s cool (per IPC‑7530 practices). A 7–10 top‑zone oven with closed‑loop conveyor speed fits most mixes; nitrogen helps wetting on ENIG/OSP and reduces BGA/QFN voiding. Validate with thermocouples on low/medium/high thermal‑mass sites.

Wave or selective for mixed technology?

If ≥60% of THT joints share orientation and keep‑outs are generous, wave soldering (lead‑free pot ~255–265 °C, 2–4 s contact, top‑side preheat 110–130 °C) wins on throughput. Dense SMT near connectors favors selective solder: nitrogen, local preheat, 3–8 mm nozzles, and ~1–3 s per pin plus moves—often the takt driver unless you buffer.

DFM knobs that make machines faster

• Fiducials: 1.0 mm bare‑copper dot, 2.0 mm mask clearance; three global, local pairs near <0.5 mm pitch

• Panel rails: 5 mm edges; V‑score residual 0.3–0.4 mm/side; keep copper ≥1.0 mm from score

• Tabs: mouse‑bite Ø0.6 mm, 1.0 mm pitch, 0.5 mm web; support tall parts during depanel

• Orientation: lock 0/90°; align tape pin‑1 to panel flow to reduce nozzle swaps and vision time

• Packaging: favor 8 mm tape for chips; reserve trays for large QFN/BGA/odd‑form

• Test pads: ≥1.0 mm pad, ≥0.5 mm mask relief; ≥1.5 mm from board edge for fixture clearance

Data and line integration you should require

Provide machine‑ready data: Gerber X2 or IPC‑2581/ODB++, centroid (XYRS), stack‑up, and paste apertures. Use SMEMA or IPC‑HERMES‑9852 for conveyor handshakes and IPC‑CFX (IPC‑2591) for telemetry, traceability, and live OEE. Daily PM should cover feeder/nozzle calibration and conveyor‑width verification to keep repeatability inside spec.

Inspection coverage and acceptance targets

Post‑reflow AOI should verify polarity, presence, value, and fillets; AXI quantifies hidden joints and voiding on QFN/BGA. Align acceptance to IPC‑A‑610 Class 2 or Class 3 early so stencil apertures, reflow margins, and inspection rules match your quality target.

What do prototypes actually need?

For <25 boards with ≤800 placements/board at 0402–0.5 mm pitch, a single flexible placer with ~8–15k real CPH, a manual or semi‑auto printer, and a 7–9 zone oven is cost‑effective. Add inline SPI/AOI and a chip shooter when you cross ~20k placements/lot, introduce 01005/0.4 mm pitch, or your takt target drops below ~50 s/board.

HyperPCB capabilities relevant to your build

HyperPCB operates an ISO 9001:2015 certified QMS (SGS certificate CN‑2023‑Q1156, valid to June 2027). We return quotes within 24 hours and DFM feedback within 1 business day. Builds can be inspected to IPC Class 2 or Class 3 acceptance criteria, and we support RoHS and REACH for hazardous substance control.

Decision checkpoint

Compute placements/board × boards/hour, then pick equipment whose measured (not catalog) CPH is at least 1.2–1.3× that load, with placement accuracy matched to your tightest pitch and a reflow profile proven on your thermal extremes. Lock fiducials, rails, and apertures early so the line hits spec without constant intervention.