Why your custom ATmega328P board won’t connect to ISP (and how to fix)

An ATmega328P usually won’t enter ISP because reset, power/AVCC, clock, or SPI wiring is wrong, or the programmer SCK is too fast; here’s how to isolate it.

Quick triage checklist

• Verify 6-pin ICSP pinout and orientation: 1=MISO, 2=VCC, 3=SCK, 4=MOSI, 5=RESET, 6=GND

• Confirm solid power and ground; tie AVCC to VCC and decouple both

• Ensure RESET can be pulled low by the programmer (no heavy loads on RESET)

• Slow the programmer SCK to ≤ target fclk/4

• Check voltage levels (3.3 V vs 5 V) match programmer I/O levels

• Disconnect peripherals from MOSI/MISO/SCK and test again

Is the ICSP header wired correctly?

Miswired ICSP headers are the top cause. The standard 6-pin ISP maps to: 1=MISO, 2=VCC, 3=SCK, 4=MOSI, 5=RESET, 6=GND. Many custom boards rotate the header; confirm pin 1 (triangle/notch/silkscreen dot) and the ribbon cable key. Use a continuity check from header to the ATmega328P pins per the datasheet; do not rely on Arduino pin labels when using the TQFP package. If series resistors are used on MOSI/MISO/SCK, keep them small (0–100 Ω) and avoid large RC loads on SCK that round edges.

Is the target actually powered?

ISP requires a stable rail at the target. Power the board from its regulator or let the programmer provide VCC if it supports it—but never both without coordination. Decouple each VCC/AVCC pin with 100 nF ceramic placed within a few millimeters, plus 10–47 µF bulk nearby. Tie AVCC to VCC (directly or via a ferrite bead) even if you don’t use ADC; leave AREF with a 100 nF to GND if you’re not feeding an external reference. If brown-out fuses are set (e.g., 2.7 V or 4.3 V), a marginal rail will cause continuous resets; verify with a scope or a DMM under load.

Reset line mistakes block ISP

RESET must be pulled up (10 kΩ typical) and be directly drivable low by the programmer. Common blockers:

• A large capacitor from RESET to GND (tens to hundreds of nF) without a series resistor will slow edges and fight the programmer. If you use auto-reset from a USB-UART, keep the classic 100 nF from DTR to RESET but ensure a 10 kΩ pull-up and avoid extra capacitance.

• Strong pull-ups (<4.7 kΩ), ESD clamps to VCC, or transistor networks on RESET can keep the line from reaching a valid low.

• If the RSTDISBL fuse was set, the RESET pin becomes I/O and ISP is disabled; recovery needs high-voltage programming (12 V on RESET).

Programmer SCK too fast for the target clock?

The ISP SCK must be ≤ fclk/4. A blank ATmega328P ships with the 8 MHz internal RC and CKDIV8 enabled, so fclk = 1 MHz; SCK must be ≤ 250 kHz. Many programmers default above that. Solutions:

• For avrdude with a bitbang-capable tool (e.g., USBasp), use: avrdude -c usbasp -p m328p -B 10 to get ~100 kHz SCK (B is µs/bit; 10 → 100 kHz)

• Some USBasp have a “slow” jumper; enable it for initial fuse work

• If you fused the chip to an external crystal/clock and none is present, provide a temporary clock on XTAL1/CLKI (1–8 MHz) to regain access and fix fuses

Voltage level mismatches cause silent failures

Match programmer I/O to the target supply. A 5 V programmer into a 3.3 V 328P can latch-up or simply not meet VIH/VIL. If your board is 3.3 V, use a 3.3 V-capable programmer or level shifting on MOSI/SCK/RESET and ensure MISO does not back-drive the programmer.

Are peripherals loading the SPI lines?

Displays, radios, SD cards, and LEDs on MOSI/MISO/SCK can hold lines, add capacitance, or drive against the programmer. During bring-up, isolate peripherals (remove jumpers, depopulate 0 Ω links, or lift CS lines so they’re inactive). Avoid placing LEDs directly on SCK; if you must, buffer or use ≥10 kΩ so the LED load does not distort SCK.

Check the device signature and part selection

A healthy connection returns the ATmega328P signature 0x1E 0x95 0x0F. If avrdude reports a different signature, confirm you selected the correct part (-p m328p vs -p m328), the wiring is correct, and the clock/SCK speed rules are met. Do not use -F to force unless you’re only probing; fix the root cause first.

Minimal bring-up that always programs

For a fresh board, start with the bare essentials:

• VCC per your design (5 V or 3.3 V), GND

• AVCC tied to VCC; 100 nF at each VCC/AVCC pin, 10–47 µF bulk

• 10 kΩ RESET pull-up; no large C to GND on RESET

• 6-pin ICSP wired MISO/VCC/SCK/MOSI/RESET/GND as per the AVR pinout

• No crystal required initially (factory default runs from internal RC); add crystal + 2×22 pF later if needed

This configuration eliminates 90% of board-specific interference.

Oscilloscope sanity checks

While invoking a read (e.g., avrdude -c usbasp -p m328p), you should see SCK toggling (tens to hundreds of kHz), MOSI activity, RESET held low, and MISO responding with bursts. No SCK means the programmer/cable/PC is at fault; SCK without MISO activity points to wiring, level, or fuse/clock issues.

When only high-voltage programming will recover it

If SPIEN was cleared or RSTDISBL set, ISP is disabled. Use an HV programmer (HVPP/HVSP, 12 V on RESET) to re-enable SPIEN and restore RESET. After that, ISP will work normally.

Manufacturing note

For production, keep the ICSP header short-trace and away from heavy switching edges, allow optional 0–100 Ω series resistors on SPI to tune ringing, and provide DNP jumpers to isolate peripherals during programming. HyperPCB can build and inspect boards to IPC Class 2 or Class 3, and we operate under an ISO 9001:2015 certified QMS (SGS CN-2023-Q1156, valid to June 2027).