ESP32 unused pins and EMI control: what to tie, float, and damp

What should I do with unused ESP32 pins?

Tie every unused input to a defined level (47–100 kΩ), leave unused outputs unconnected but drive them to a steady logic level in firmware, and add 22–33 Ω source series resistors on fast GPIOs to cut edge‑rate EMI.

Strapping pins and boot behavior

Boot/strapping pins must be at documented defaults at reset; enforce with 10–47 kΩ external pulls. Avoid adding >100 pF total to any strapping net to prevent slow edges at POR. Keep each strapping trace under ~25 mm and at least 5 mm from switching nodes or clock lines. If UART0 TX/RX are routed off‑board for logging/flash, place 22–33 Ω series resistors within 1–2 mm of the ESP32 pins and keep the run to a connector under ~50 mm unless shielded.

How to park digital inputs and outputs?

Unused digital inputs: give each a bias with 47–100 kΩ to VDD or GND; internal pulls in ESP32 silicon are typically tens of kilo‑ohms, but external parts are preferred where noise or coupling is present. Unused outputs: leave the pads unconnected on the PCB and configure the GPIOs as outputs at a constant level (commonly logic 0) early in boot to avoid toggling.

Analog‑capable or multiplexed pins

If a GPIO defaults to an ADC function you are not using, disable the analog function in firmware and keep the pad biased as a digital input (47–100 kΩ). If a nominally analog input is left unrouted, tie it to ground through ~100 kΩ to avoid mid‑rail pickup.

How to control edge‑rate EMI on GPIO?

Broadband emissions scale with edge rate, not just clock frequency: f_high ≈ 0.35/tr. A 1 ns edge contains energy up to ~350 MHz. Add 22–33 Ω source damping within 1–2 mm of the driver pin on any net that does not require sub‑nanosecond edges. For I/O reaching a cable or external connector, place a compact snubber near the connector (22–51 Ω in series with 100–330 pF to ground). Use common‑mode chokes only where ESD/cable standards require them. Keep a continuous return under all high dV/dt traces and do not cross split planes.

RF feed and antenna keep‑out

Respect the module’s vendor keep‑out. If no guidance is given, reserve 10–15 mm copper‑free clearance in all layers around the antenna aperture, and remove ground under the radiating element. Route the feed as 50 Ω. On FR‑4 (Er ≈ 4.2) with 1.6 mm thickness and 35 µm copper, an outer‑layer microstrip for 50 Ω is roughly 3.0 ± 0.3 mm wide; on 0.8 mm boards it is ~1.4 ± 0.2 mm. Verify with a field solver or IPC‑2141 equations using your final stack‑up. Add a π‑matching footprint (shunt–series–shunt) at the antenna port with 0 Ω/NC placeholders for tuning. Stitch ground along the RF trace with vias at 2–3 mm pitch and keep the line short and away from DC‑DC nodes.

Power integrity without sabotaging EMI

Place 0.1 µF decouplers within 1–2 mm of each ESP32 supply pin and a local ~1 µF within ~5 mm per rail segment. Keep the DC‑DC inductor and SW node at least 10–15 mm from the antenna; when possible, bury SW on an inner layer with an uninterrupted ground plane on the adjacent layer. A 4‑layer stack (L1 signals/RF, L2 solid GND, L3 power, L4 signals) reduces loop area and improves return paths.

Verification before certification

Do a pre‑scan with a near‑field probe and spectrum analyzer to find radiating nets (boot UART, long GPIOs, converters). Confirm RF feed impedance with TDR or a VNA if you deviated from the module’s reference layout. Derive line widths from IPC‑2141 or a 2D/3D solver, then lock the stack‑up with your fabricator.

Manufacturing and compliance options

Boards can be built and inspected to IPC Class 2 or Class 3, and RoHS/REACH substance control is supported. Our quality management system is ISO 9001:2015 certified (SGS, certificate CN‑2023‑Q1156, valid to June 2027). Quotes are returned within 24 hours and DFM feedback within 1 business day. For RF work, our partner factory manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies.

Checklist you can paste into your review

• Strapping pins: 10–47 kΩ to required defaults; no >100 pF loads; trace <25 mm and >5 mm from switch/clock nets

• No floating inputs (47–100 kΩ bias); unused outputs driven constant and left unconnected

• Off‑board I/O: 22–33 Ω at source; add 22–51 Ω + 100–330 pF snubber at connector if needed

• Antenna keep‑out enforced; RF feed 50 Ω verified against final stack‑up; π‑match footprint present

• Decouplers within 1–2 mm; DC‑DC SW confined and ≥10–15 mm from antenna; solid return under fast nets

• Pre‑scan hotspots fixed before filing (e.g., FCC Part 15/EN 300 328)