What catches engineers off guard during PCB assembly?

The most common surprises are BOM and rotation mismatches, unclear polarity/Pin 1 marks, stencil–paste choices that spike defects, MSL handling gaps, weak panelization, and missing test access.

BOM and rotation mismatches — how do they happen?

Small naming drifts create big fallout. Typical failure modes:

• XY centroids use a different rotation convention (assembler expects CCW 0/90/180/270 but CAD exported CW). Always state rotation convention, units (mm), origin, and board side per file.

• Alternate PN in BOM doesn’t match the land pattern (QFN vs. QFN-EP variant). Lock package codes, not just manufacturer names.

• DNPs left as POS=1 in the placement file. Keep a single source of truth for population.

Provide: RefDes, X, Y, Rot, Side, MPN, and a readme defining units/origin and rotation.

Polarity and Pin 1 marking clarity

Diodes need a silkscreen cathode bar that aligns with the package mark; electrolytics need a clear “+” near the positive pad. For ICs, combine a Pin 1 triangle on silkscreen with a copper chamfer or dot. For BGAs and QFNs: follow IPC‑7351 conventions and keep mask and legend away from pads. Typical mask clearance around NSMD BGA pads: 0.05–0.075 mm.

Stencil, paste type, and tombstoning

Choose stencil thickness by the smallest pitch on the board:

• 4 mil (100 µm) for 0.5 mm pitch QFN/QFP and 0201/0402 passives; Type 4 paste for small apertures.

• 5–6 mil (125–150 µm) for 0603/0805 with no fine‑pitch ICs.

Apply 10–20% aperture reductions and rounded rectangles on chip resistors/caps to cut tombstoning. BTC (QFN) pads: use windowpane apertures; target voiding consistent with IPC‑7093 guidance (<50% area is a common acceptance aim; set your own spec upfront).

Fiducials, panel rails, and depanelization

Global fiducials: three 1.0 mm bare‑copper dots with 2.0 mm solder‑mask clearance, asymmetric placement. Add local fiducials for fine‑pitch/BGA regions. Provide 5–10 mm panel rails on long edges with two 3.0 mm tooling holes per rail. Keep parts ≥5 mm from V‑score or tab‑route; V‑score web 0.3–0.5 mm is typical. Define whether breakoff is V‑score or mouse‑bites and place tabs away from tall or fragile parts.

Moisture sensitive devices — are you counting floor life?

MSL3+ parts expire quickly on the floor (J‑STD‑033). If seals are broken or time is exceeded, baking (e.g., 125 °C for up to 24 h, per device ratings) may be required. Document paste alloy (e.g., SAC305), desired reflow peak (often 235–245 °C per J‑STD‑020 class), and keep thermally massive shields/heatsinks off until after reflow when possible.

Via‑in‑pad, solder wicking, and BGAs

Unfilled via‑in‑pad under BGAs and BTCs will wick paste and cause opens/voids. Specify filled and capped VIP for BGA pads, and use NSMD land patterns for BGAs per IPC‑7095. Provide X‑ray inspection notes for fine‑pitch BGAs if required.

Test points and programming access — do you have enough?

Budget pogo targets early: 0.9–1.0 mm exposed pads, ≥1.27 mm pitch, with solder mask between pads. Provide a stable ground target and orient all targets in a grid if ICT is planned (100 mil grid common). For programming, reserve a standard SWD 2×5 1.27 mm or a Tag‑Connect footprint and confirm pinout in the assembly notes. Clearly state whether no‑clean flux residues are acceptable under low‑standoff BTCs; if not, call out cleaning.

Supply chain surprises from reels to alternates

Reel leader/trailer length matters for automated feeders (budget ~300–400 mm each end or order full reels). Cut tape can add handling cost and risk. Track lifecycle (Active/NRND) and PCNs; pre‑approve vetted alternates at BOM release to avoid on‑the‑fly substitutions. Record date/lot codes when traceability is required.

Data package quality checklist

Before release, confirm:

• Gerbers/ODB++ with paste layers, board outline, and readme of stackup and copper weights

• XY centroid with units, origin, rotation convention, side, RefDes map

• BOM with exact MPNs, approved alternates, and DNPs synchronized to XY

• Assembly drawing with polarity/Pin 1, height callouts, no‑place zones, and coating keepouts

• Stencil spec (thickness, aperture tweaks), reflow profile target, flux/cleaning requirements

• Panel drawing with rails, fiducials, depanelization method, and component edge clearances

Acceptance criteria and regulatory needs

State the target acceptance: IPC Class 2 or Class 3 for inspection and testing. If hazardous substance control is required, specify RoHS and REACH compliance in the purchase documents. Refer to IPC‑A‑610/J‑STD‑001 for solder acceptance language to avoid ambiguity.

How HyperPCB reduces these risks

• We can build and inspect to IPC Class 2 or IPC Class 3 acceptance criteria, matching the standard you specify [5].

• RoHS and REACH compliance is supported when you require hazardous substance control [6].

• Quotes are returned within 24 hours and DFM feedback within 1 business day, so mismatches in XY/BOM/stencil are flagged before build [2].

• Our quality management system is ISO 9001:2015 certified (certificate CN‑2023‑Q1156 by SGS, valid to June 2027) [1].

• Our partner factory AEGIS maintains ISO 9001:2015, ISO 14001:2015, ISO 45001:2018, plus ISO 13485:2016 and IATF 16949, supporting regulated medical and automotive documentation needs [3][4].

• For RF programs, our partner manufactures its own high‑frequency laminates and supplies RF PCB fabricators in China, including publicly listed PCB companies, helping stabilize material planning [7].