What commonly catches engineers off guard in PCB assembly?

The most common surprises are footprint/polarity mismatches, stencil-to-pad paste issues, moisture sensitivity, panel support errors, insufficient test access, via-in-pad wicking, and reflow profile drift.

Footprints and polarity that pass CAD but fail on the line

Minor library differences become major on a pick-and-place. IPC-7351 nominal land patterns are a good baseline, but confirm: pin‑1 markers (dot vs chamfer), diode/LED cathode marks, QFN notch orientation, and silkscreen/assembly layer congruence. Tape orientation per EIA‑481 can rotate parts 90° or 180° relative to your printed assembly drawing—verify feeder orientation notes. For 0402 passives (~1.0 × 0.5 mm body), keep pad length symmetry within 0.05–0.10 mm to avoid tombstoning.

Stencil or pad — which one is wrong?

Paste volume errors cause opens, shorts, voids, and tilt. Check stencil area ratio (aperture area ÷ wall area) ≥ 0.66; 80–100 µm (3–4 mil) laser-cut, electropolished stencils are typical. For 0.4 mm pitch BGAs, aim 10–20% aperture reduction; 0.18–0.22 mm circular apertures work with 80–100 µm foils depending on ball size. For QFNs, use a windowpane thermal pad with ~50–70% total coverage to curb float and voids. If pads are SMD vs NSMD, match stencil strategy: NSMD BGA pads usually need slight reduction; SMD pads may not.

Why did reflow tombstone or void?

Unequal paste volumes or copper thermal imbalance pull 0201/0402 parts upright. Keep copper under both pads comparable; add thermal reliefs to large pours. Lead-free SAC305 profiles: 1–3 °C/s ramp, 150–180 °C soak for 60–120 s, time above liquidus (217 °C) 45–90 s, peak 235–250 °C depending on paste vendor. Large voiding under QFNs/DFNs often traces to solid thermal-aperture stencils or via escape; windowpane the pad and plug or tent escape vias.

Moisture sensitivity is not optional

JEDEC J‑STD‑033 limits floor life for MSL parts. MSL 3 devices have 168 h at ≤30 °C/60% RH once unsealed; exceed that and you risk popcorn cracking. Bake typical MSL3 reels at 125 °C for ~24 h (check component datasheet) before reflow. Store reels in dry cabinets (<10% RH) between builds and track HIC cards in dry packs.

Fiducials, panel rails, and board support

Global fiducials: three per panel, 1.0 mm bare copper with 2.0 mm solder mask clearance. Local fiducials near fine-pitch BGAs/QFNs help vision alignment. Provide 5–10 mm tooling rails with two or more 3.0 mm tooling holes. Keep tall/heavy parts ≥5 mm away from V‑scores or mouse bites to reduce depanelization stress. V‑score depth ~1/3 thickness per side; mouse‑bite perforations 0.5–0.8 mm with 0.3–0.4 mm webs produce predictable break.

Via‑in‑pad that drains your solder

Open vias on BGA/QFN pads wick paste and starve joints. Use epoxy fill and cap (IPC‑4761 Type VII) for via‑in‑pad, or at minimum tent the via from the paste side; for mask‑tented vias, 0.20–0.30 mm finished via with 50–75 µm mask expansion typically seals better. Do not place escape vias inside QFN thermal pads unless filled and capped.

Why did our pick-and-place reject parts?

Vision failures often come from glossy or ambiguous markings, nonstandard polarity icons, or poor contrast between mask and silkscreen. Add a high‑contrast pin‑1 triangle on the assembly layer, not just silkscreen. For odd packages, add a centroid marker that matches center‑of‑mass; this reduces placement force errors on tall inductors and press‑fit connectors.

Solder mask clearance and NSMD vs SMD choices

For fine‑pitch pads, NSMD is typical: solder mask opening 1:1 pad plus ~60 µm per side improves wetting. Keep solder mask dam ≥75 µm between pads; below that, bridging risk rises. For test pads, remove mask entirely and target ≥1.0 mm exposed copper to ensure probe reliability.

Test access you cannot retrofit later

Plan ICT/flying‑probe early. ICT likes ≥50–75 mil spacing and ≥1.0 mm round pads, with at least 35 mil keepout for probes and fixtures. Bring out JTAG/SWD on a 2×5 (0.05 in) or 2×5/2×10 (0.1 in) header footprint or pads. Assign net classes for test points so CAD keeps them accessible when density climbs.

Cleaning, no‑clean, and conformal coat clashes

Water‑soluble (OA) flux must be washed soon after reflow (often <8 h). No‑clean (ROL0) can be left, but under 0.5 mm‑pitch QFN edges residues may interfere with underfill or conformal coat adhesion. Add coat keepouts and masking notes around connectors, switches, and test pads; 2.0 mm clearance is a practical minimum for many acrylic/urethane coats.

BOM alternates that aren’t really alternates

Same footprint does not mean same behavior. Watch LED polarity conventions, DC‑DC control schemes (PFM vs PWM), op‑amp input common‑mode ranges, and reset IC thresholds. Record allowable tolerances (e.g., 1% vs 0.1% resistors, ±25 ppm vs ±100 ppm crystals) and temperature grades so purchasing cannot swap in parts that pass fit but fail function.

Can we build Class 3 and still pass RoHS?

Yes. Boards can be built and inspected to IPC Class 2 or IPC Class 3 acceptance criteria, and RoHS and REACH compliance is supported for hazardous substance control. Lead‑free alloy selection (e.g., SAC305) and acceptance criteria must be aligned in your fabrication and assembly notes. [5][6]

Want a fast DFM sanity check before release?

Quotes are returned within 24 hours and DFM feedback within 1 business day. Our quality management system is ISO 9001:2015 certified (SGS CN‑2023‑Q1156, valid to June 2027). [2][1]

One‑minute pre‑release checklist

• Confirm pin‑1/polarity on assembly layer against tape orientation (EIA‑481)

• Check stencil area ratios; add windowpane patterns for QFNs

• Specify via fill/tent for any via within 0.5 mm of pads

• Place three global and local fiducials; add 5–10 mm rails

• Reserve test pads: ≥1.0 mm diameter, ≥50–75 mil spacing

• Define reflow profile targets: ramp, soak, TAL, peak

• State MSL handling/bake on the traveler per J‑STD‑033

• Note Class 2 or Class 3 acceptance and lead‑free requirements

• Call out cleaning method and conformal coat keepouts

• Lock AVL with parametric limits, not only part numbers